Quantum Motion attends APS March Meeting 2026: Who, What, Where, and When

George Ridgard
Senior IC Validation Engineer

The drive to create utility-scale fault-tolerant quantum computers will require higher qubit densities and scalable control electronics. As many qubit platforms operate at deep-cryogenic temperatures, the use of cryo-electronics close to or even monolithically integrated with qubit chips for control functions presents a promising approach to address cryostat wiring bottlenecks. However, this introduces thermal management challenges, necessitating accurate thermal models of qubit chips. Inputs to these models include the thermal conductivities of key materials and thermal boundary resistances between chips and the thermal bath, which must be experimentally derived.

Here, we present a novel method to extract substrate thermal conductivity and chip-to-cold-plate thermal boundary resistance as a function of temperature. We demonstrate this using a multiplexed array of thermometer diodes and on-chip heaters in a 22-nm FDSOI node. The diodes are used to extract on-chip temperature as a function of heater distance, heater power, and bath temperature from 300 mK to 4 K. Using this data, we extract the relevant thermal material properties and apply these values to a 3D FEM thermal solver to generate a thermal heatmap for arbitrary on-chip power distributions. This work paves the way for more accurate thermal models of the quantum system at deep cryogenic temperature, which in turn will help to facilitate greater qubit densities and more complex integrated cryo-CMOS.

Simon Benjamin
CSO

Fault-tolerant quantum computers use decoders to monitor for errors and find a plausible correction. A decoder may also output 'soft information' in the form of a decoder confidence score (DCS) to gauge its success. One example is swim distance, computed from the shortest path between syndrome clusters. Such a score can be used in diverse ways to enhance the performance of quantum computers.

For shallow circuits, it is trivial to exploit a DCS simply by aborting an unpromising execution: for a distance-13 surface code under circuit-level noise, rejecting a mere 0.1% of possible DCS values improves the entire circuit's logical error probabiliy (LEP) by more than 5 orders of magnitude. For larger algorithms comprising up to billions of decoding windows one can use a (sufficiently accurate) DCS to assign each circuit's output a unique LEP, and use it as a basis for maximum likelihood estimation. This can reduce the effects of noise by an order of magnitude at no quantum cost.

Moving beyond these filtering and inference methods, a DCS can be used as a more radical enabler: it can make possible forms of logical representation and processing that would otherwise be infeasible due to the risk of correlated errors. I will illustrate this in the context of an approach to silicon spin quantum computing.

Felix von Horstig
Senior Quantum Engineer

As arrays of spin qubits based on quantum dots (QDs) continue to scale, a detailed understanding of how device parameters vary across arrays is required to accurately design large quantum processors. Such efforts are needed to produce a quantum equivalent to the classical process design kit in the various QD manufacturing platforms being established. QD characterisation at scale has gained increasing attention in the field by making use of cryo-wafer probers (Si/SiGe), as well as cryogenic time-domain multiplexing (Si FDSOI) and device matrix arrays using shared control (Ge).

In this work, we present a quantum device matrix array (QDMA), fabricated in a 300mm Si MOS, and consisting of many unit cells of a single electron box (SEB) + double quantum dot (DQD). The array is controlled using a combination of on- and off-chip multiplexing and shared control lines. We use this platform for device process control, compare dot parameters across different QD dimensions, and to develop auto-tuning routines. These routines are both necessary for characterisation of the array and for the initialisation of larger quantum processors.

We make use of automated tune-up routines designed to minimise the required measurements needed to tune-up the sensor dot and DQD electron occupation of the device. We characterise the QDs in terms of their lever arm matrix, addition energies, tunnel rates and couplings and compare the measurements with simulations of the unit cells.

Isobel Clarke
Quantum Engineer, UCL

Constructing a quantum computer capable of broad and important applications is likely to require millions of addressable physical qubits, posing the challenge of large-scale integration of quantum systems with classical electronics. Fully depleted silicon-on-insulator CMOS technology has been used to develop a range of cryogenic electronic components for the control and readout of different qubit modalities interfaced on separate chips. However, recent measurements of quantum dots on this technology raise the tantalising prospect of realising control electronics and spin qubits on the same manufacturing platform, within a single integrated circuit (IC). In our work, we demonstrate single-shot spin readout in addressable quantum dot devices within an IC fabricated using industry-standard 22nm fully depleted silicon-on-insulator technology. We achieve spin-to-charge conversion via a ramped energy-selective measurement, detected using a radio-frequency single-electron transistor and addressed by on-chip cryogenic electronics. The observation of consistent readout visibilities exceeding 90% and millisecond spin relaxation times in two nominally identical devices within the addressable array supports the reproducibility of the unit cell. The successful observation of spin readout using this CMOS process marks a key step towards realising highly scalable and integrated spin qubits.

Simon Benjamin
CSO

Semiconductor devices present unique opportunities for fault tolerant, large scale quantum computing. The prospect of fast and high fidelity shuttling is particularly exciting. I’ll focus on two shuttling-based paradigms and I’ll use the surface code as the example protocol, although the methods are not limited to this. In the looped pipeline approach multiple qubits move in closed cycles - remarkably, this allows an effective 3D architecture although the physical device is 2D. This can be very helpful in routing information, and for supporting otherwise-impossible codes. A more radical paradigm is “snakes on a plane” which reformats logical qubits into 1D entities that can then move freely over a 2D lattice. This creates a vulnerability that can be tackled using a powerful resource called decoder confidence (a.k.a. decoder soft information). All these ideas are compatible both with single-electron physical qubits and with singlet/triplet encoding, the latter bringing the advantage of ‘erasure conversion’.

Jack Turner
Quantum Software Engineer

There have been extensive theoretical studies and high-fidelity experimental demonstrations of shuttling in Si/SiGe^1,2, but considerably less work has been done on this topic in Si/SiO2. To address this, we build on previous 2D simulation work³, by performing full 3D modelling of conveyor-mode charge shuttling in realistic Si/SiO2 devices with charged defects, gate imperfections, and roughness at the oxide interface. Using solutions to the Poisson and time-dependent Schrödinger equations for different shuttling speeds and gate voltages, we find that positive defects directly in the shuttling path capture passing electrons when using lower clavier gate voltages of 250mV. Increasing the conveyor confinement with gate voltages of 500mV ensures the passing electrons escape the trap, but they emerge in an orbitally excited state potentially opening spin-flip pathways via spin-orbit coupling and phonon relaxation.

On the other hand, single negative defects don’t disrupt transport by knocking electrons into adjacent minima, but do induce orbital excitation for lower clavier gate voltages. These excitations are suppressed by increasing the confinement, and so are not expected to present an obstacle to charge shuttling.

Our simulations also show charge shuttling remains robust against 30% variations in clavier gate footprint and interface roughness as high as rms=0.9nm. However, when we use these modelling tools to compute the valley splitting and phase for different interfaces, we find that even modest roughness creates adversarial valley landscapes with low splitting and rapidly changing phase. We observe that the electron is highly susceptible to valley excitations when shuttling across these interfaces for even slow shuttling speeds, which may lead to spin-dephasing and leakage out of the computational subspace. This highlights the importance of mitigation strategies currently being explored in the Si/SiGe literature to Si/SiO2 devices, for example using variable shuttling speeds and paths or compensating for channel-specific dephasing with Z-rotations.⁴

[1] Langrock et al. (2023)
[2] De Smet et al. (2025)
[3] Jeon et al. (2025)
[4] Oda et al. (2024)

Christian Binder
Quantum Theorist, University of Oxford

Building a silicon spin quantum computer is a vast optimisation problem - spanning chip architecture, operating regimes, shuttling protocols, and two-qubit gate choice and design. Navigating this landscape demands simulation tools that are not only comprehensive but computationally efficient enough to be practically useful.

We present VirtualLab, an end-to-end quantum device simulation framework developed at Quantum Motion. Starting directly from a GDS layout file, VirtualLab constructs the 3D electrostatic environment via a Green's function Poisson solver, enabling rapid potential evaluation across gate voltage space. This feeds into a Schrödinger solver supporting single- and multi-electron systems, including valley physics, spin-orbit coupling, full configuration interaction, and time-dependent effects. The framework is designed to be platform-agnostic — with minor adjustments it can target Si/SiO₂, Si/SiGe, and hole-spin devices.

We demonstrate the full pipeline on realistic device geometries, tracking the system from the single-electron regime all the way to the strongly correlated limit, where Wigner molecule formation reshapes the valley, orbital, and exchange structure. We further showcase the time-dependent capabilities of the framework, simulating dynamical protocols such as electron shuttling — illustrating how VirtualLab can serve as a versatile virtual testbed across the full stack of device operation.