Written by: Tom Bromley, Applications Lead and April Carniol, VP Technology Strategy
Quantum Motion is integrating with the newly announced NVIDIA CUDA-Q Logical orchestration layer for fault tolerant compilation, targeting our unique silicon spin systems. Silicon-based quantum computing modalities leverage mature semiconductor manufacturing infrastructure to enable high-precision production, while silicon spin qubits gain a distinct connectivity edge through electron shuttling – physically sliding individual electrons across the chip to link components without a dense web of wires. Through flexible, long-range connections across the chip, shuttling supports rich quantum error correction architectures [2, 3], including faster logical operations and more efficient qubit encodings, requiring far fewer total qubits. To visualise this, the figure below shows how our looped pipeline architecture allows the usual 2D surface code layout to be stacked three-dimensionally, with fast transversal gates along the virtual-z direction.
Quantum Motion’s looped pipeline architecture realises surface code stacking using shuttling multiple qubits within a single loop. Intra-loop interactions are fast, allowing for transversal operations between surface code layers.
Successful execution of algorithms requires a careful compilation of circuit-level instructions onto a target architecture. This can be a challenging task for circuits designed to tackle utility-scale problems, requiring billions of operations to be orchestrated on thousands of logical qubits. Moreover, the beneficial features of silicon spin architectures result in additional complexities in the compilation process. In our looped pipeline example, the compiler should be aware of faster connectivity in virtual-z direction and may place regularly interacting qubits within the same stack.
The expansion of NVIDIA CUDA-Q’s open source platform to add a logical orchestration layer addresses the challenges of QEC-aware compilation: instead of a time-consuming manual compilation, we simply define a target architecture and some key logical primitives before automatically breaking down to hardware-level instructions. We are excited to integrate CUDA-Q Logical within Quantum Motion’s fault tolerant compilation pipeline, realising the following benefits:
- Faster and more automated: allowing us to explore compilation of a wider range of logical circuits, useful for algorithm design and use case exploration.
- Exact and iterative: a detailed circuit breakdown improves upon previous painstaking and necessarily approximate manual estimates and enables iterative improvements to the circuit design and compilation process.
- Hardware compatible: CUDA-Q Logical can output instructions in the industry-standard quantum intermediate representation (QIR) format, providing a natural pathway to integrate fault tolerant compilation with Quantum Motion hardware.
Quantum Motion’s next steps will be to represent the looped pipeline layout within CUDA-Q Logical, giving access to fast, transversal two-qubit gates for logical qubits within the same stack. We also continue to work on logical compilation of quantum chemistry problems as part of our QUICHE and state preparation collaborations, aiming for tighter integration with the CUDA-Q platform and the ultimate goal of end-to-end compilation of commercially-impactful problems such as FeMoco.